Production Data
WM8213
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 24MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Reset-Level Clamp (RLC) circuit/ Reference Level DAC
RLC switching impedance
50
2
Ω
mA
Ω
VRLC short-circuit current
VRLC output resistance
2
VRLC Hi-Z leakage current
Reference RLCDAC resolution
Reference RLCDAC step size
VRLC = 0 to AVDD
1
µA
bits
4
VRLCSTEP
AVDD=3.3V
0.173
V/step
V/step
V
RLCDACRNG=0
RLCDACRNG=1
Reference RLCDAC step size
VRLCSTEP
VRLCBOT
0.11
0.4
Reference RLCDAC output
voltage at code 0(hex)
AVDD=3.3V,
RLCDACRNG=0
Reference RLCDAC output
voltage at code 0(hex)
VRLCBOT
VRLCTOP
VRLCTOP
RLCDACRNG=1
0.4
3.0
V
V
V
Reference RLCLDAC output
voltage at code F(hex)
AVDD=3.3V,
RLCDACRNG=0
Reference RLCDAC output
voltage at code F(hex)
RLCDACRNG = 1
2.05
RLCDAC
RLCDAC
DNL
INL
-0.5
+0.5
LSB
LSB
+/-1
Offset DAC, Monotonicity Guaranteed
Resolution
8
bits
LSB
Differential non-linearity
Integral non-linearity
Step size
DNL
0.1
0.5
1
INL
0.25
2.04
-260
+260
LSB
mV/step
mV
Output voltage
Code 00(hex)
Code FF(hex)
mV
Programmable Gain Amplifier
Resolution
9
bits
V/V
7.34
Gain equation
0.66 +
* PGA[8 : 0]
511
Max gain, each channel
Min gain, each channel
Channel Matching
GMAX
GMIN
8
V/V
V/V
%
0.66
1
5
Analogue to Digital Converter
Resolution
16
2
bits
MSPS
V
Speed
24
Full-scale input range
(2*(VRT-VRB))
LOWREFS=0
LOWREFS=1
1.2
V
PD Rev 4.0 July 2007
7
w