WM8198
Production Data
INPUT VIDEO SAMPLING
tPER
tMCLKH tMCLKL
MCLK
tVSMPH
tVSMPSU
VSMP
INPUT
tVSU
tVH
tRSU
tRH
VIDEO
Figure 1 Input Video Timing
Note:
1.
See Page 14 (Programmable VSMP Detect Circuit) for video sampling description.
Test Conditions
AVDD = DVDD1 = 5.0, DVDD2 = 3.3, AGND = DGND = 0V, TA = 25°C unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
MCLK period
tPER
83.3
ns
MCLK high period
MCLK low period
tMCLKH
tMCLKL
tVSMPSU
tVSMPH
tVSU
37.5
37.5
10
5
ns
ns
ns
ns
ns
ns
ns
ns
VSMP set-up time
VSMP hold time
Video level set-up time
Video level hold time
Reset level set-up time
Reset level hold time
15
5
tVH
tRSU
15
5
tRH
Notes:
1.
2.
t
VSU and tRSU denote the set-up time required after the input video signal has settled.
Parameters are measured at 50% of the rising/falling edge.
OUTPUT DATA TIMING
MCLK
tPD
OP[7:0]
Figure 2 Output Data Timing
PD Rev 4.0 June 2004
9
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
