WM8198
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = 5.0, DVDD2 = 3.3, AGND = DGND = 0V, TA = 25°C, MCLK = 12MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)
Conversion Rate
HIGHSPEED = 0,
HIGHSPEED = 1, MCLK = 24MHz
Max Gain
6
MSPS
MSPS
Vp-p
Vp-p
Vp-p
Vp-p
V
12
0.4
4.08
0.6
3
Full-scale input voltage range,
PGAMODE=0. (see Note 1)
Min Gain
Full-scale input voltage range,
PGAMODE=1. (see Note 1)
Max Gain
Min Gain
Input signal limits (see Note 2)
Full-scale transition error
VIN
0
AVDD
Gain = 0dB;
PGA[8:0] = 96(hex)
20
20
mV
Zero-scale transition error
Gain = 0dB;
mV
PGA[8:0] = 96(hex)
Differential non-linearity
Integral non-linearity
Total output noise
DNL
INL
1.25
20
LSB
LSB
Min Gain
Max Gain
3.9
11
LSB rms
LSB rms
%
Channel to channel gain matching
References
1
Upper reference voltage
VRT
VRB
VRX
VRTB
2.85
1.35
1.65
1.5
V
V
V
V
Ω
Lower reference voltage
Input return bias voltage
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
VRLC output resistance
1.4
1.6
1
50
2
Ω
mA
Ω
2
VRLC Hi-Z leakage current
RLCDAC resolution
VRLC = 0 to AVDD
AVDD = 5.0V
1
µA
4
bits
V/step
V/step
V
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
VRLCSTEP
VRLCSTEP
VRLCBOT
0.25
0.17
0.39
RLCDAC output voltage at
AVDD = 5.0V
code 0(hex), RLCDACRNG = 0
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
VRLCTOP
VRLCTOP
0.26
4.14
2.81
25
V
V
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
AVDD = 5.0V
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
V
VRLC deviation
mV
Offset DAC, Monotonicity Guaranteed
Resolution
8
bits
LSB
Differential non-linearity
Integral non-linearity
Step size
DNL
INL
0.1
0.5
1
0.25
2.04
-260
+260
LSB
mV/step
mV
Output voltage
Code 00(hex)
Code FF(hex)
mV
Notes:
1.
2.
Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
PD Rev 4.0 June 2004
6
w