Production Data
WM8152
REGISTER
BIT
NO
BIT
NAME(S)
DEFAULT
DESCRIPTION
Setup
Register 5
0
VSMPDET
0
0 = Normal operation, signal on VSMP input pin is applied directly to
Timing Control block.
1 = Programmable VSMP detect circuit is enabled. An internal
synchronisation pulse is generated from signal applied to VSMP input pin
and is applied to Timing Control block.
3:1
VDEL[2:0]
000
When VSMPDET = 0 these bits have no effect.
When VSMPDET = 1 these bits set a programmable delay from the
detected edge of the signal applied to the VSMP pin. The internally
generated pulse is delayed by VDEL MCLK periods from the detected
edge.
See Figure 14, Internal VSMP Pulses Generated for details.
4
POSNNEG
0
When VSMPDET = 0 this bit has no effect.
When VSMPDET = 1 this bit controls whether positive or negative edges
are detected:
0 = Negative edge on VSMP pin is detected and used to generate internal
timing pulse.
1 = Positive edge on VSMP pin is detected and used to generate internal
timing pulse.
See Figure 14 for further details.
Test
7
TCLK
0
0 = Normal Operation, OP[3:0] output ADC data.
Register 1
1 = Internal Clock Test Mode. This allows internal timing signals to be
multiplexed onto the OP[3:0] pins as follows.
PIN
TCLK=0
OP[3]
OP[2]
OP[1]
OP[0]
TCLK=1
INTVSMP
OP[3]
OP[2]
OP[1]
OP[0]
Video sample clock
ADC clock
Reset sample clock
Offset DAC
(Red)
7:0
7:0
7:0
7:0
DACR[7:0]
DACG[7:0]
DACB[7:0]
DAC[7:0]
80
80
80
Red channel offset DAC value. Used under control of the INTM[1:0]
control bits.
Offset DAC
(Green)
Green channel offset DAC value. Used under control of the INTM[1:0]
control bits.
Offset DAC
(Blue)
Blue channel offset DAC value. Used under control of the INTM[1:0]
control bits.
Offset DAC
(RGB)
A write to this register location causes the red, green and blue offset DAC
registers to be overwritten by the new value
PGA gain
(Red)
7:0
7:0
7:0
7:0
PGAR[7:0]
PGAG[7:0]
PGAB[7:0]
PGA[7:0]
0
0
0
Determines the gain of the red channel PGA according to the equation:
Red channel PGA gain = [0.78+(PGAR[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
PGA gain
(Green)
Determines the gain of the green channel PGA according to the equation:
Green channel PGA gain = [0.78+(PGAG[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
PGA gain
(Blue)
Determines the gain of the blue channel PGA according to the equation:
Blue channel PGA gain = [0.78+(PGAB[7:0]*7.57)/255]. Used under
control of the INTM[1:0] control bits.
PGA gain
(RGB)
A write to this register location causes the red, green and blue PGA gain
registers to be overwritten by the new value
Table 5 Register Control Bits
PD Rev 4.0 January 2004
23
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
