Production Data
WM8152
OPERATING MODE TIMING DIAGRAMS
The following diagrams show 4-bit multiplexed output data and MCLK, VSMP and input video
requirements for operation of the most commonly used modes as shown in Table 3. The diagrams
are identical for both CDS and non-CDS operation.
16.5 MCLK PERIODS
MCLK
VSMP
VINP
OP[3:0]
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C D
(DEL = 00)
OP[3:0]
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
D
(DEL = 01)
OP[3:0]
(DEL = 10)
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
B
OP[3:0]
A
B C
A
B
C
D
A
B
C
D
A
B
C
D
A
C D
D
(DEL = 11)
Figure 15 Mode 1 Operation
23.5 MCLK PERIODS
MCLK
VSMP
VINP
OP[3:0]
C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D
C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D
(DEL = 00)
OP[3:0]
(DEL = 01)
OP[3:0]
C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D
C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D A B A B C D
(DEL = 10)
OP[3:0]
(DEL = 11)
Figure 16 Mode 2 Operation
PD Rev 4.0 January 2004
19
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
