Production Data
WM2631
Test Characteristics:
RL = 10kΩ, CL = 100pF AVDD = DVDD = 5V ± 10%, VREF = 2.048V and AVDD = DVDD = 3V ± 10%, VREF = 1.024V over
recommended operating free-air temperature range (unless noted otherwise).
TEST
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
CONDITIONS
Reference Configured as Input
Reference input resistance
Reference input capacitance
Reference feedthrough
RREF
CREF
50
10
kΩ
pF
dB
V
REF=2VPP at 1kHz
-84
+ 2.048V DC, DAC code 0
Reference input bandwidth
V
REF= 0.4VPP + 2.048V DC,
DAC code 512
Slow
1.9
2.2
MHz
MHz
Fast
Reference Configured as Output
Low reference voltage
High reference voltage
Output source current
Output sink current
Load Capacitance
PSRR
VREFOUTL
VREFOUTH
IREFSRC
1.010
2.020
1.024
2.048
1.040
2.096
1
V
V
VDD > 4.75V
mA
mA
µF
dB
IREFSNK
-1
1
in parallel with 100nF cap.
10
60
Digital Inputs
High level input current
Low level input current
Input capacitance
Notes:
IIH
IIL
CI
Input voltage = DVDD
Input voltage = 0V
-1
-1
1
1
µA
µA
pF
8
1. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding
the effects of zero code and full scale errors).
2. Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change
of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same
direction (or remains constant) as a change in digital input code.
3. Zero code error is the voltage output when the DAC input code is zero.
4. Gain error is the deviation from the ideal full-scale output excluding the effects of zero code error.
5. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the
proportion of this signal imposed on the zero code error and the gain error.
6. Zero code error and Gain error temperature coefficients are normalised to full-scale voltage.
7. Output load regulation is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ
load. It is expressed as a percentage of the full scale output voltage with a 10kΩ load.
8.
I
DD is measured while continuously writing a digital code of 512 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V
supply current will increase.
9. Slew rate results are for the lower value of the rising and falling edge slew rates.
10. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and
falling edges. Limits are ensured by design and characterisation, but are not production tested.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 April 2001
5
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
