Production Data
WM2629
SERIAL INTERFACE
INTERFACE MODES
The control interface can operate in two different modes:
•
•
In the microcontroller mode, FS needs to be held low until all 16 data bits have been
transferred. If FS is driven high before the 16th falling clock edge, the data transfer is cancelled.
The DAC is updated after a rising edge on FS.
In DSP mode, FS only needs to stay low for 20ns, and can go high before the 16th falling clock
edge.
SCLK
FS
DIN
X
D15 D14
D1
D0
X
E15 E14
E1
E0
X
X
F15 F14
Figure 7 Interface Timing in Microcontroller Mode
SCLK
FS
DIN
X
D15 D14
D1
D0 E15 E14
E1
E0
X
X
X
F15 F14
Figure 8 Interface Timing in DSP Mode
The operating mode is selected using pin 17 (MODE).
MODE PIN (17)
HIGH
INTERFACE MODE
Microcontroller
DSP mode
LOW or unconnected
Table 2 Interface Mode Selection
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the interface timing. The maximum serial clock rate is:
1
fSCLK max
=
= 31MHz
tWH min + tWLmin
Since a data word contains 16 bits, the sample rate is limited to
1
fs max
=
=1.95MHz
16(
tWH min + tWL min
)
However, the DAC settling time to 8 bits accuracy limits the response time of the analogue output for
large input step transitions.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
9
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
