Production Data Rev 1.0
WM2616
DEVICE DESCRIPTION
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input
voltage and the input code according to the following relationship:
CODE
Output voltage = 2
(
VREFIN
)
4096
INPUT
OUTPUT
4095
4096
1111
1111
1111
(
REF
)
)
2 V
:
:
2049
4096
1000
1000
0111
0000
0001
0000
1111
2
(V
REF
2048
4096
0000
1111
2
(
V
REF
)
= VREF
2047
(
REF
)
2 V
4096
:
:
1
0000
0000
0000
0001
0000
2
(V
REF
)
4096
0000
0V
Table 1 Binary Code Table (0V to 2VREFIN Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2kW
load with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent of code.
The REFIN pin has an input resistance of 10MW and an input capacitance of typically 5pF. The
reference voltage determines the DAC full-scale output.
SERIAL INTERFACE
Explanation of data transfer:
First, the device has to be enabled with NCS set to low. Then, a falling edge of FS starts shifting the
data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits
have been transferred, the next rising edge on SCLK or FS causes the content of the shift register to be
moved to the DAC latch which updates the voltage output to the new level.
The serial interface of the device can be used in two basic modes:
·
·
four wire (with chip select)
three wire (without chip select)
Using chip select (four wire mode), it is possible to have more than one device connected to the serial
port of the data source (DSP or microcontroller). If there is no need to have more than one device on the
serial bus, then NCS can be tied low.
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
1
fSCLKmax =
= 20MHz
tWCH min+ tWCL min
The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC settling
time to 12 bits limits the update rate for large input step transitions.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
7
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
