WAN_0143
INTERFACE TIMING
MASK
Frames
(SYNC)
t DEL
t DEL
AUXADC Conversion
(MASK = 11)
Conv
Conv
Conv
Conv
t DEL
t DEL
AUXADC Conversion
Conv
Delay
Delay
Delay
Conv
Delay
(MASK = 10)
AUXADC Conversion
Conv
Delay
Conv
Delay
Conv
Delay
Conv
(MASK = 01)
Figure 1 MASK Delay Timings (tDEL = 2 frames)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Frame Delay set by register 76h
tDEL
0
288
frames
MASK
BCLK
SYNC
tSETUP
t HOLD
tSETUP
t HOLD
Figure 2 MASK Delay Timings
PARAMETER
SYMBOL
tSETUP
MIN
162.8
81.4
TYP
MAX
UNIT
ns
Setup time from MASK edge to SYNC 1
Hold time of MASK level from SYNC
rising edge.
tHOLD
ns
Note:
1. There must be at least two BCLK's between the rising edge of MASK and the rising edge of SYNC. Therefore, once MASK is
high there must be at least two BCLK rising edges prior to the SYNC pulse.
Rev 1.0 March 2004
w
3
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
