W9825G6KH
10.4 Mode Register Set Cycle
tRSC
CLK
tCMS
tCMS
tCMH
tCMH
CS
RAS
CAS
WE
tCMS
tCMS
tAS
tCMH
tCMH
tAH
Register
set data
A0-A12
BS0,1
next
command
Burst Length
A0
A1
A2
A3
A4
A5
A6
Sequential
A2 AA10 A0
Interleave
Burst Length
0
0
0
0
1
1
1
1
A00
A00
A10
A10
A00
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Addressing Mode
CAS Latency
"0" (Test Mode)
A0
0
Reserved
Full Page
Reserved
A10
A10
Addressing Mode
A03
0
1
Sequential
Interleave
A07
A8
"0"
Reserved
WriteAM0 ode
CAS Latency
Reserved
Reserved
2
A6 AA50 A4
0
0
0
0
1
A00
A00
A10
A10
A00
0
1
0
1
0
A9
A10
AA101
A12
BS0
BS1
"0"
"0"
3
Reserved
Reserved
"0"
"0"
Single Write Mode
Burst read and Burst write
Burst read and single write
A90
0
1
"0"
* "Reserved" should stay "0" during MRS cycle.
Publication Release Date: Sep. 01, 2014
Revision: A02
- 20 -
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