W9412G6JH
11.6 Mode Register Set (MRS) Timing
CLK
CLK
tMRD
CMD
ADD
MRS
NEXT CMD
Register Set data
Burst Length
A0
A1
A2
A2
0
A1
0
A0
0
Sequential
Interleaved
Burst Length
Addressing Mode
CAS Latency
Reserved
Reserved
0
0
1
2
4
8
2
4
8
0
1
0
0
1
1
A3
A4
1
0
0
1
0
1
Reserved
Reserved
1
1
0
A5
A6
A7
A8
1
1
1
Addressing Mode
A3
0
Sequential
Interleaved
Reserved
"0"
1
DLL Reset
CAS Latency
Reserved
A6
0
A5
0
A4
0
"0"
"0"
"0"
"0"
"0"
A9
0
0
1
A10
A11
BA0
BA1
Reserved
2
0
1
0
3
4
0
1
1
1
0
0
Reserved
2.5
Mode Register Set
or
Extended Mode
Register Set
1
0
1
1
1
0
Reserved
1
1
1
DLL Reset
No
A8
0
* "Reserved" should stay "0" during MRS cycle.
Yes
1
MRS or EMRS
Regular MRS cycle
Extended MRS cycle
BA1
BA0
0
0
1
1
0
1
0
1
Reserved
Publication Release Date: Nov. 29, 2011
Revision A03
- 39 -
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