W90N745CD/W90N745CDG
6.2 System Manager
6.2.1 Overview
The W90N745 system manager has the following functions.
y
y
y
y
y
y
y
System memory map
Data bus connection with external memory
Product identifier register
Bus arbitration
PLL module
Clock select and power saving control register
Power-On setting
6.2.2 System Memory Map
W90N745 provides 2G bytes cacheable address space and the other 2G bytes are non-cacheable. The
On-Chip Peripherals bank is on 1M bytes top of the space (0xFFF0_0000 – 0xFFFF_FFFF) and the On-
Chip RAM bank’s start address is 0xFFE0.0000, the other banks can be located anywhere (cacheable
space:0x0000_0000~0x7FDF_FFFF
0x8000_0000~0xFFDF_FFFF).
if
Cache
ON;
non-cacheable
space:
The size and location of each bank is determined by the register settings for “current bank base address
pointer” and “current bank size”. Please note that when setting the bank control registers, the address
boundaries of consecutive banks must not overlap.
Except On-Chip Peripherals and On-Chip RAM, the start address of each memory bank is not fixed. You
can use bank control registers to assign a specific bank start address by setting the bank’s base pointer
(13 bits). The address resolution is 256K bytes. The bank’s start address is defined as “base pointer <<
18” and the bank’s size is “current bank size”.
In the event of an access requested to an address outside any programmed bank size, an abort signal is
generated. The maximum accessible memory size of each external IO bank is 4M bytes (by word
format), and 64M bytes on each SDRAM bank.
Publication Release Date: September 22, 2006
- 25 -
Revision A2
WINBOND [ WINBOND ]
