W90N745CD/W90N745CDG
6. FUNCTIONAL DESCRIPTION
6.1 ARM7TDMI CPU CORE
The ARM7TDMI CPU core is a member of the Advanced RISC Machines (ARM) family of general-
purpose 32-bit microprocessors, which offer high performance for very low power consumption. The
architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are much simpler than those of micro-programmed Complex Instruction Set
Computers. Pipelining is employed so that all parts of the processing and memory systems can operate
continuously. The high instruction throughput and impressive real-time interrupt response are the major
benefits.
The ARM7TDMI CPU core has two instruction sets:
(1) The standard 32-bit ARM set
(2) A 16-bit THUMB set
The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM core
while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit
registers. THUMB instructions operate with the standard ARM register configuration, allowing excellent
interoperability between ARM and THUMB states. Each 16-bit THUMB instruction has a corresponding
32-bit ARM instruction with the same effect on the processor model.
ARM7TDMI CPU core has 31 x 32-bit registers. At any one time, 16 sets are visible; the other registers
are used to speed up exception processing. All the register specified in ARM instructions can address
any of the 16 registers. The CPU also supports 5 types of exception, such as two levels of interrupt,
memory aborts, attempted execution of an undefined instruction and software interrupts.
A[31:0]
Address Register
Scan Control
Address
Incrementer
Instruction Decoder
Register Bank
Control Logic
(31 x 32-bit registers)
(6 status registers)
32 x8 Multiplier
Instruction Pipeline
Read Data Register
Thumb Instruction Decoder
Barrel Shifter
Writer Data
Register
32-bit ALU
D[31:0]
Figure 6.1.1 ARM7TDMI CPU Core Block Diagram
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