W90N745CD/W90N745CDG
BITS
DESCRIPTION
FrameIntervalToggle
31
FINTVT
This bit is toggled by HCD when it loads a new value into Frame Interval.
FSLargestDataPacket
[30:16]
[15:14]
[13:0]
FSLDP
Reserved
FINTV
This field specifies a value that is loaded into the Largest Data Packet
Counter at the beginning of each frame.
Reserved. Read/Write 0's
Frame Interval
This field specifies the length of a frame as (bit times - 1). For 12,000 bit
times in a frame, a value of 11,999 is stored here.
Host Controller Frame Remaining Register
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
HcFmInterval
0xFFF0_5038
R
Host Controller Frame Remaining Register 0x0000_0000
31
FRMT
23
30
29
28
27
26
25
24
Reserved
22
14
6
21
13
5
20
12
4
19
Reserved
18
10
2
17
9
16
8
15
11
Reserved
FRM
7
3
1
0
FRM
BITS
DESCRIPTION
FrameRemainingToggle
[31]
FRMT
Loaded with FrameIntervalToggle when Frame Remaining is loaded.
Reserved. Read/Write 0's
[30:14]
Reserved
Frame Remaining
When the Host Controller is in the USBOPERATIONAL state, this 14-bit field
decrements each 12 MHz clock period. When the count reaches 0, (end of
frame) the counter reloads with Frame Interval. In addition, the counter
loads when the Host Controller transitions into USBOPERATIONAL.
[13:0]
FRM
- 182 -
WINBOND [ WINBOND ]
