W90N745CD/W90N745CDG
5. PIN DESCRIPTION
Table 5.1 W90N745 Pins Description
DESCRIPTION
PIN NAME
IO TYPE
Clock & Reset
EXTAL (15M)
XTAL (15M)
nRESET
JTAG Interface
TMS
I
15MHz External Clock / Crystal Input
O
IS
15MHz Crystal Output
System Reset, active-low
IUS
IUS
O
JTAG Test Mode Select, internal pull-up with 70K ohm
JTAG Test Data in, internal pull-up with 70K ohm
JTAG Test Data out
TDI
TDO
TCK
IDS
IUS
JTAG Test Clock, internal pull-down with 58K ohm
JTAG Reset, active-low, internal pull-up with 70K ohm
nTRST
External Bus Interface
A [20:18]
A [17:0]
O
Address Bus (MSB) of external memory and IO devices.
Address Bus of external memory and IO devices.
Data Bus (LSB) of external memory and IO device.
Write Byte Enable for specific device (nECS [1:0]).
Data Bus Mask signal for SDRAM (nSCS [1:0]), active-low.
SDRAM chip select for two external banks, active-low.
Row Address Strobe for SDRAM, active-low.
IOS
IOS
D [15:0]
nWBE [1:0] /
SDQM [1:0]
nSCS [1:0]
nSRAS
IOS
O
O
O
O
O
O
nSCAS
Column Address Strobe for SDRAM, active-low.
SDRAM Clock Enable, active-high
MCKE
nSWE
SDRAM Write Enable, active-low
MCLK
System Master Clock Out, SDRAM clock, output with slew-rate control
nWAIT /
External Wait, active-low. This pin indicates that the external devices need
more active cycle during access operation.
IUS
GPIO[30] /
nIRQ3
General Programmable In/Out Port GPIO[30]. If memory and IO devices in EBI
do not need wait request, it can be configured as GPIO[30] or nIRQ3.
nBTCS
nECS [3:0]
nOE
O
IO
O
ROM/Flash Chip Select, active-low.
External I/O Chip Select, active-low.
ROM/Flash, External Memory Output Enable, active-low.
Publication Release Date: September 22, 2006
- 13 -
Revision A2
WINBOND [ WINBOND ]
