W83697HF/F
Bit 5-3: Reflect the IRQ resource assigned for ECP port.
cnfgB[5:3]
000
IRQ resource
reflect other IRQ resources selected by PnP register (default)
001
IRQ7
010
IRQ9
011
IRQ10
IRQ11
IRQ14
IRQ15
IRQ5
100
101
110
111
Bit 2-0: These five bits are at high level during a read and can be written.
6.3.10 ecr (Extended Control Register) Mode = all
This register controls the extended ECP parallel port functions. The bit definitions are follows:
7
6
5
4
3
2
1
0
empty
full
service Intr
dmaEn
nErrIntrEn
MODE
MODE
MODE
Bit 7-5: These bits are read/write and select the mode.
000
001
Standard Parallel Port mode. The FIFO is reset in this mode.
PS/2 Parallel Port mode. This is the same as 000 except that direction may be used
to tri-state the data lines and reading the data register returns the value on the data
lines and not the value in the data register.
010
011
Parallel Port FIFO mode. This is the same as 000 except that bytes are written or
DMAed to the FIFO. FIFO data are automatically transmitted using the standard
parallel port protocol. This mode is useful only when direction is 0.
ECP Parallel Port Mode. When the direction is 0 (forward direction), bytes placed into
the ecpDFifo and bytes written to the ecpAFifo are placed in a single FIFO and auto
transmitted to the peripheral using ECP Protocol. When the direction is 1 (reverse
direction), bytes are moved from the ECP parallel port and packed into bytes in the
ecpDFifo.
100
101
110
Selects EPP Mode. In this mode, EPP is activated if the EPP mode is selected.
Reserved.
Test Mode. The FIFO may be written and read in this mode, but the data will not be
transmitted on the parallel port.
111
Configuration Mode. The confgA and confgB registers are accessible at 0x400 and
0x401 in this mode.
Publication Release Date: Feb. 2002
- 74 -
Revision 0.70
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