W83697HF/F
6.2 ENHANCED PARALLEL PORT (EPP).......................................................................................................................... 64
6.2.1 Data Swapper...........................................................................................................................................................65
6.2.2 Printer Status Buffer................................................................................................................................................65
6.2.3 Printer Control Latch and Printer Control Swapper .......................................................................................66
6.2.4 EPP Address Port.....................................................................................................................................................66
6.2.5 EPP Data Port 0-3...................................................................................................................................................67
6.2.6 Bit Map of Parallel Port and EPP Registers......................................................................................................67
6.2.7 EPP Pin Descriptions..............................................................................................................................................68
6.2.8 EPP Operation.........................................................................................................................................................68
6.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT.............................................................................................. 69
6.3.1 ECP Register and Mode Definitions....................................................................................................................69
6.3.2 Data and ecpAFifo Port..........................................................................................................................................70
6.3.3 Device Status Register (DSR) ................................................................................................................................70
6.3.4 Device Control Register (DCR) ............................................................................................................................ 71
6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010...................................................................................................72
6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011............................................................................................................72
6.3.7 tFifo (Test FIFO Mode) Mode = 110...................................................................................................................72
6.3.8 cnfgA (Configuration Register A) Mode = 111 .................................................................................................72
6.3.9 cnfgB (Configuration Register B) Mode = 111 .................................................................................................72
6.3.10 ecr (Extended Control Register) Mode = all ...................................................................................................73
6.3.11 Bit Map of ECP Port Registers............................................................................................................................ 74
6.3.12 ECP Pin Descriptions...........................................................................................................................................75
6.3.13 ECP Operation.......................................................................................................................................................76
6.3.14 FIFO Operation .....................................................................................................................................................76
6.3.15 DMA Transfers........................................................................................................................................................77
6.3.16 Programmed I/O (NON-DMA) Mode .................................................................................................................77
6.4 EXTENSION FDD MODE (EXTFDD)............................................................................................................................ 77
6.5 EXTENSION 2FDD MODE (EXT2FDD)........................................................................................................................ 77
7.
8.
9.
GENERAL PURPOSE I/O...........................................................................................78
ACPI REGISTERS FEATURES .................................................................................81
HARDWARE MONITOR ..........................................................................................82
9.1 GENERAL DESCRIPTION ............................................................................................................................................... 82
9.2 ACCESS INTERFACE...................................................................................................................................................... 82
Publication Release Date: Feb. 2002
- III -
Revision 0.70
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