W83697HF/F
3.2.6 Data Rate Register (DR Register) (Write base address + 4)...........................................................................40
3.2.7 FIFO Register (R/W base address + 5)................................................................................................................41
3.2.8 Digital Input Register (DI Register) (Read base address + 7)....................................................................... 44
3.2.9 Configuration Control Register (CC Register) (Write base address + 7)....................................................45
4.
UART PORT.................................................................................................................46
4.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B) ........................................... 46
4.2 REGISTER ADDRESS ...................................................................................................................................................... 46
4.2.1 UART Control Register (UCR) (Read/Write).....................................................................................................46
4.2.2 UART Status Register (USR) (Read/Write).........................................................................................................48
4.2.3 Handshake Control Register (HCR) (Read/Write)...........................................................................................50
4.2.4 Handshake Status Register (HSR) (Read/Write)...............................................................................................51
4.2.5 UART FIFO Control Register (UFR) (Write only).............................................................................................52
4.2.6 Interrupt Status Register (ISR) (Read only)....................................................................................................... 53
4.2.7 Interrupt Control Register (ICR) (Read/Write) .................................................................................................54
4.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) ..............................................................................54
4.2.9 User-defined Register (UDR) (Read/Write)........................................................................................................55
5.
CIR RECEIVER PORT...............................................................................................56
5.1 CIR REGISTERS ................................................................................................................................................................ 56
5.1.1 Bank0.Reg0- Receiver Buffer Registers (RBR) (Read) ....................................................................................56
5.1.2 Bank0.Reg1- Interrupt Control Register (ICR) ................................................................................................56
5.1.3 Bank0.Reg2- Interrupt Status Register (ISR) ....................................................................................................56
5.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)........................57
5.1.5 Bank0.Reg4- CIR Control Register (CTR) .........................................................................................................58
5.1.6 Bank0.Reg5- UART Line Status Register (USR) ..............................................................................................59
5.1.7 Bank0.Reg6- Remote Infrared Config Register (RIR_CFG) ...........................................................................59
5.1.8 Bank0.Reg7- User Defined Register (UDR/AUDR) ..........................................................................................60
5.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) .....................................................................................61
5.1.10 Bank1.Reg2- Version ID Regiister I (VID) ....................................................................................................... 62
5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) .....................62
5.1.12 Bank1.Reg4- Timer Low Byte Register (TMRL)..............................................................................................62
5.1.13 Bank1.Reg5- Timer High Byte Register (TMRH) ............................................................................................ 62
6.
PARALLEL PORT......................................................................................................63
6.1 PRINTER INTERFA CE LOGIC........................................................................................................................................ 63
Publication Release Date: Feb. 2002
- II -
Revision 0.70
WINBOND [ WINBOND ]
