W83697HF
2. LPC (LOW PIN COUNT) INTERFACE
LPC interface is to replace ISA interface serving as a bus interface between host (chip-set) and peripheral
(Winbond I/O). Data transfer on the LPC bus are serialized over a 4 bit bus. The general characteristics of
the interface implemented in Winbond LPC I/O are:
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One control line, namely LFRAME#, which is used by the host to start or stop transfers. No peripherals
drive this signal.
The LAD[3:0] bus, which communicates information serially. The information conveyed are cycle type,
cycle direction, chip selection, address, data, and wait states.
MR (master reset) of Winbond ISA I/O is replaced with a active low reset signal, namely LRESET#, in
Winbond LPC I/O.
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An additional 33 MHz PCI clock is needed in Winbond LPC I/O for synchronization.
DMA requests are issued through LDRQ#.
Interrupt requests are issued through SERIRQ.
Power management events are issued through PME#.
Comparing to its ISA counterpart, LPC implementation saves up to 40 pin counts free for integrating more
devices on a single chip.
The transition from ISA to LPC is transparent in terms of software which means no BIOS or device driver
update is needed except chip-specific configuration.
Publication Release Date:Feb. 2002
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Revision 0.70
WINBOND [ WINBOND ]
