W83697HF/F
Bit 1
Bit 0
: CIRIRQEN.
= 0
SMI PME
interrupt due to CIR's IRQ.
disable the generation of an
/
= 1
SMI PME
enable the generation of an
/
interrupt due to CIR's IRQ.
: MIDIIRQEN.
= 0
SMI PME
disable the generation of an
/
interrupt due to MIDI's IRQ.
interrupt due to MIDI's IRQ.
= 1
SMI PME
enable the generation of an
/
CRF9 (Default 0x00)
Bit 7- 3 : Reserved. Return zero when read.
Bit 2
: PME_EN: Select the power management events to be either an PME or SMI interrupt for
the IRQ events. Note that: this bit is valid only when SMIPME_OE = 1.
= 0
= 1
SMI
the power management events will generatean
event.
the power management events will generate an PME event.
Bit 1
Bit 0
: FSLEEP: This bit selects the fast expiry time of individual devices.
= 0 1 S
= 1 8 mS
SMI
PME
output enable bit.
: SMIPME_OE: This is the
and
PME
will be generated. Only the IRQ status bit is set.
= 0
SMI
neither
nor
= 1
an SMI or PME event will be generated.
10.14 Logical Device B (Hardware Monitor)
CR30 (Default 0x00)
Bit 7- 1 : Reserved.
Bit 0
= 1 Activates the logical device.
= 0 Logical device is inactive.
CR60, CR 61 (Default 0x00, 0x00)
These two registers select Hardware Monitor base address [0x100:0xFFF] on 8-byte boundary.
CR70 (Default 0x00)
Bit 7- 4 : Reserved.
Bit 3- 0 : These bits select IRQ resource for Hardware Monitor.
Publication Release Date: Feb. 2002
- 156 -
Revision 0.70
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