W83627HF/ F/ HG/ G
CR23 （Default 0x00）
BIT
DESCRIPTION
7 - 1
0
Reserved.
IPD （Immediate Power Down）. When set to 1, it will put the whole chip into power
down mode immediately.
CR24 （Default 0b1s000s0s）
BIT
DESCRIPTION
7
EN16SA
0： 12 bit Address Qualification
1： 16 bit Address Qualification
CLKSEL
6
0： The clock input on Pin 1 should be 24 Mhz.
1： The clock input on Pin 1 should be 48 Mhz.
The corresponding power-on setting pin is SOUTB （pin 83）.
5 - 3 Reserved
2
ENKBC（Read Only）
0： KBC is disabled after hardware reset.
1： KBC is enabled after hardware reset.
This bit is set/reset by power-on setting pin SOUTA（pin 54）.
Reserved
1
0
PNPCVS
0： The Compatible PnP address select registers have default values.
1： The Compatible PnP address select registers have no default value.
When trying to make a change to this bit, new value of PNPCVS must be complemen-
tary to the old one to make an effective change. For example, the user must set
PNPCVS to 0 first and then reset it to 1 to reset these PnP registers if the present value
of PNPCVS is 1. The corresponding power-on setting pin is NDTRA （pin 52）.
CR25 （Default 0x00）
BIT
DESCRIPTION
7 - 6
Reserved
5
4
URBTRI. UART2 output pin tri-stated.
URATRI. UART1 output pin tri-stated.
PRTTRI. Parallel port output pin tri-stated.
Reserved
3
2 - 1
0
FDCTRI. FDC output pin tri-stated.
- 82 -
WINBOND [ WINBOND ]
