W83601R/G
7.2 W83601R/G REGISTER DESCRIPTIONS
CR00 (GP Port 1: Input port Data Register, Default 0x--, Read Only)
This register is a data port for input only. It reflects the incoming logic levels of the pins defined as an
input mode by CR03. The data will be inverted by CR02.
Bit 7 ~ 0: GP17 ~ GP10 Input Data Port.
CR01 (GP Port 1: Output port Data Register, Default 0x00, Read/Write)
This register is a data port for output only. It reflects the outgoing logic levels of the pins defined as an
output mode by CR03. This register will reflect the value of output Flip-flop during a read access. The
output data style will be inverted or changed by CR02 or CR04.
Bit 7 ~ 0: GP17 ~ GP10 Output Data Port.
CR02 (GP Port 1: Polarity Inversion Register, Default 0xf0, Read / Write)
This register enables polarity inversion of pins defined as input or output by CR03.
When set to "1", the incoming/outgoing port value is inverted.
When set to "0", the incoming/outgoing port value is the same as in data register.
Bit 7 ~ 0: GP17 ~ GP10 Polarity Inversion Register.
CR03 (GP Port 1: Input/Output Configuration Register, Default 0xff, Read / Write)
This register selects Input or Output mode of pins.
When set to "1", respective GPIO port is programmed as an input port.
When set to "0", respective GPIO port is programmed as an output port.
Bit 7 ~ 0: GP17 ~ GP10 Input/Output Configuration Register.
CR04 (GP Port 1: Output Style Control Register, Default 0x00, Read / Write)
This register selects Output style of pins as level or pulse.
When set to "1", respective GPIO port is programmed as a pulse signal.
When set to "0", respective GPIO port is programmed as a level signal.
Bit 7 ~ 0: GP17 ~ GP10 Output Style Control Register.
CR05 (GP Port 1: Input latched data Register, Default 0x--, Read Only)
This register will latch Port 1 data while power on or RST# pin low, which is controlled by CR14h bit 0.
Bit 7 ~ 0: GP17 ~ GP10 Input latched data.
CR06-07 Reserved Register
Publication Release Date: December 12, 2007
- 7 -
Revision 1.2
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