W83601R/G
8. FUNCTION DESCRIPTIONS
8.1 ACCESS INTERFACE
The W83601R/G provides a two-wired serial interface which is compliant with SMBusTM 1.0 Write Byte
and Read Byte protocol.
8.1.1 Write a data into the W83601R/G register
0
0
7
8
0
7
8
SCL
SDA
0
1
1
A2
A1
A0
R/W
0
D7
D6
D5
D4
D3
D2
D1
D0
Start By
Master
Ack
by
601R
Ack
by
601R
Frame 1
Serial Bus Address Byte
Frame 2
Internal Index Register Byte
7
8
SCL (Continued)
SDA (Continued)
D7
D6
D5
D4
D3
D2
D1
D0
Ack
by
601R
Stop
by
Master
Frame 3
Data Byte
8.1.2 Read a data from the W83601R/G register
0
0
7
8
0
4
7
8
SCL
SDA
...
...
0
1
1
A2
A1
A0
R/W
0
D7
D6
D5
D4
D3
D2
D1
D0
Start By
Master
Ack
by
601R
Ack
by
601R
Frame 1
Serial Bus Address Byte
Frame 2
Pointer Byte
0
0
7
8
0
7
8
SCL (Cont..)
SDA (Cont..)
0
1
1
A2
A1
A0
R/W
1
D7
D6
D5
D4
D3
D2
D1
D0
Repea
Start
By
No Ack
by
Master
Ack
by
601R
Stop by
Master
Frame 3
Serial Bus Address Byte
Frame 4
MSB Data Byte
Master
Publication Release Date: December 12, 2007
Revision 1.2
- 11 -
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