W83195WG-382/W83195CG-382
STEPLESS FOR ATI K8 CLOCK GENERATOR
SRCT/ ATIG output state in during POWER
DOWN assertion.
1: Driven (2*Iref)
0: Tristate (Floating)
SRCT/ ATIG output state in during STOP Mode
assertion.
5
DRI_CONT
0
R/W
1: Driven (6*Iref)
0: Tristate (Floating)
Complementary parts always tri-state (floating) in
power down or stop mode.
4
3
Reserved
1
1
R/W
R/W
Reserved
CPU align with HTT
1 : Enable
CPU2HTT_SYNC
0 : Disable
2
1
AZSKEW<2>
AZSKEW<1>
1
0
CPU1 to HTT66 skew control.
Skew resolution is 300ps
R/W
The decision of skew direction is same as
ASKEW<2:0> setting
0
AZSKEW<0>
0
7.17 Register 16: ( Default : 24h )
AFFECTED PIN/
FUNCTION NAME(S)
BIT
PWD
FUNCTION DESCRIPTION
TYPE
Invert the SRC phase
0: Default
7
INV_SRC
0
R/W
1: Inverse
Invert the HTT & PCI phase
0: Default
1: Inverse
6
INV_PCI
0
R/W
R/W
5
4
3
2
1
0
CSKEW<2>
CSKEW<1>
CSKEW<0>
PSKEW<2>
PSKEW<1>
PSKEW<0>
1
0
0
1
0
0
CPUCLKT1 to CPUCLKT0 skew control
Skew resolution is 300ps
The decision of skew direction is same as
CSKEW<2:0> setting
CPU1 to PCI skew control
Skew resolution is 300ps
The decision of skew direction is same as
PSKEW<2:0> setting
R/W
Publication Release Date: Feb 2006
Revision 0.6
- 13 -
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