W83195WG-382/W83195CG-382
STEPLESS FOR ATI K8 CLOCK GENERATOR
7. I
2
C CONTROL AND STATUS REGISTERS
(The register No. is increased by 1 if use byte data read/write protocol)
7.1
BIT
Register 0: ( Default : 00h )
AFFECTED PIN/
FUNCTION NAME(S)
PWD
AFFECTED PIN / FUNCTION DESCRIPTION
TYPE
7
6
5
4
3
2
SSEL<4>
SSEL<3>
SSEL<2>
SSEL<1>
SSEL<0>
EN_SSEL
0
0
0
0
0
0
Software frequency table selection through I
2
C
R/W
1
SPSPEN
0
Enable software table selection FS[4:0].
0 = Hardware table setting (Jump mode).
1 = Software table setting through Bit7~3 .
(Jumpless mode)
Enable spread spectrum mode under clock
output.
0 = Spread Spectrum mode disable
1 = Spread Spectrum mode enable
After watchdog timeout
0 = Reload the hardware FS [4:0] latched
pins setting.
1 = Reload the desirable frequency table
selection defined at Reg-5 Bit 4~0.
R/W
R/W
0
EN_SAFE_FREQ
0
R/W
7.2
BIT
Register 1: ( Default : XXh)
AFFECTED PIN/
FUNCTION NAME(S)
PWD
FUNCTION DESCRIPTION
TYPE
7
6
5
4
3
2
1
0
Reserved
CPUEN<1>
CPUEN<0>
Reserved
Reserved
FS2_BACK
FS1_BACK
FS0_BACK
1
1
1
X
X
X
X
X
Reserved
CPUCLKT1/C1 output control
1: Enable
0: Disable
CPUCLKT0/C0 output control
1: Enable
0: Disable
Reserved
Reserved
Power on latched value of FS2 pin. Default :
0
Power on latched value of FS1 pin. Default :
0
Power on latched value of FS0 pin. Default :
0
R/W
R/W
R/W
R
R
R
R
R
-6-
Publication Release Date: Feb 2006
Revision 0.6
WINBOND [ WINBOND ]
