W83194BR-97
PRELIMINARY
5.4 Register 3: 3V66 Clock Register (1 = Active, 0 = Inactive)
Bit
7
@PowerUp
Pin
34
Description
1
1
1
3V66_0(Active / Inactive)
3V66_1(Active / Inactive)
3V66_2(Active / Inactive)
FS1#
6
33
5
32
4
X
-
0
-
±
0 = 0.25% Center type Spread Spectrum Modulation
3
±
1 = 0.5% Center type Spread Spectrum Modulation
0 =
0
-
Running
2
1 = Tristate all outputs
1
0
X
X
-
-
FS3#
FS2#
5.5 Register 4: PCI Clock Additional Register (1 = Active, 0 = Inactive)
Bit
7
@PowerUp
Pin
Description
1
1
X
1
1
1
26
27
-
24_48MHz(Active / Inactive)
48MHz(Active / Inactive)
FS0#
6
5
4
22
21
20
PCICLK10 (Active / Inactive)
PCICLK9 (Active / Inactive)
PCICLK8 (Active / Inactive)
3
2
1
1
-
Reserve
0
X
-
FS4#
5.6 Register 5: Skew Register
Bit
7
@PowerUp
Pin
Description
1
0
0
1
1
1
1
1
-
-
-
-
-
-
-
-
Skew2 (CPU to 3V66 skew program bit)
6
Skew1 (CPU to 3V66 skew program bit)
5
Skew0 (CPU to 3V66 skew program bit)
4
Reserve
Reserve
Reserve
Reserve
Reserve
3
2
1
0
Publication Release Date: Dec. 1999
Revision 0.35
- 7 -
WINBOND [ WINBOND ]
