W78E365/W78E365A
Eight-source interrupt information:
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
EDGE/LEVEL
VECTOR
INTERRUPT SOURCE
ADDRESS
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
03H
0BH
13H
1BH
23H
2BH
33H
3BH
0 (highest)
IE.0
IE.1
TCON.0
1
-
2
IE.2
TCON.2
3
IE.3
-
4
IE.4
-
Timer/Counter 2
External Interrupt 2
External Interrupt 3
5
6
IE.5
-
XICON.2
XICON.6
XICON.0
XICON.3
7 (lowest)
P4CONB (C3H)
BIT
NAME
FUNCTION
00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
P43FUN1
P43FUN0
10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
7, 6
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The
address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.
Chip-select signals address comparison:
00: Compare the full address (16 bits length) with the base address register
P43AH, P43AL.
01: Compare the 15 high bits (A15−A1) of address bus with the base address
P43CMP1
P43CMP0
register P43AH, P43AL.
5, 4
10: Compare the 14 high bits (A15−A2) of address bus with the base address
register P43AH, P43AL.
11: Compare the 8 high bits (A15−A8) of address bus with the base address
register P43AH, P43AL.
P42FUN1
P42FUN0
P42CMP1
P42CMP0
The P4.2 function control bits which are the similar definition as P43FUN1,
P43FUN0.
3, 2
1, 0
The P4.2 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
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