W78C32C/W78C032C
6.3.2 Program Fetch Cycle
PARAMETER
SYMBOL
TAAS
MIN.
1 TCP-Δ
1 TCP-Δ
1 TCP-Δ
-
TYP.
MAX.
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
NOTES
Address Valid to ALE Low
Address Hold after ALE Low
-
-
4
1, 4
4
TAAH
-
-
TAPL
-
-
ALE Low to PSEN Low
PSEN Low to Data Valid
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
TPDA
TPDH
TPDZ
TALW
TPSW
-
2 TCP
1 TCP
1 TCP
-
2
0
-
3
0
-
2 TCP
3 TCP
4
4
2 TCP-Δ
3 TCP-Δ
-
PSEN Pulse Width
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "Δ" ( due to buffer driving delay and wire loading) is 20 nS.
6.3.3 Data Read Cycle
PARAMETER
ALE Low to RD Low
RD Low to Data Valid
Data Hold after RD High
Data Float after RD High
RD Pulse Width
SYMBOL
TDAR
MIN.
TYP.
MAX.
3 TCP+Δ
4 TCP
2 TCP
2 TCP
-
UNIT
nS
NOTES
1, 2
1
-
3 TCP-Δ
TDDA
-
-
nS
TDDH
0
0
-
-
nS
TDDZ
nS
TDRD
6 TCP
nS
2
6 TCP-Δ
Notes:
1. Data memory access time is 8 TCP.
2. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
- 10 -
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