W29F102
AC Characteristics, continued
Read Cycle Timing Parameters
(VDD = 5.0V ±10%, TA = 0 to 70° C)
PARAMETER
SYM.
W29F102-
45
W29F102-
50
W29F102-
55
W29F102-
70
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
TRC
TCE
TAA
TOE
TCLZ
45
-
-
50
-
-
55
-
-
70
-
-
nS
nS
nS
nS
nS
Chip Enable Access Time
Address Access Time
45
45
25
-
50
50
25
-
55
55
30
-
70
70
35
-
-
-
-
-
Output Enable Access Time
-
-
-
-
0
0
0
0
CE
OE
CE
OE
Low to Active Output
Low to Active Output
High to High-Z Output
High to High-Z Output
TOLZ
TCHZ
TOHZ
TOH
0
-
-
0
-
-
0
-
-
0
-
nS
nS
nS
nS
20
20
-
20
20
-
25
25
-
25
25
-
-
-
-
-
Output Hold from Address
Change
0
0
0
0
Write Cycle Timing Parameters
PARAMETER
Address Setup Time
Address Hold Time
SYMBOL
TAS
MIN.
TYP.
MAX.
UNIT
nS
0
50
0
-
-
-
-
-
-
TAH
nS
TCS
nS
CE
CE
WE
WE
OE
OE
CE
WE
WE
and
and
Setup Time
Hold Time
TCH
TOES
TOEH
TCP
0
0
-
-
-
-
-
-
-
-
nS
nS
nS
nS
High Setup Time
High Hold Time
Pulse Width
0
70
TWP
TWPH
TDS
70
70
50
0
-
-
-
-
nS
nS
Pulse Width
High Width
Data Setup Time
-
-
nS
Data Hold Time
TDH
TBP
-
-
nS
Word Programming Time
Erase Cycle Time
-
10
0.1
50
1
mS
TEC
-
Sec.
Note: All AC timing signals observe the following guidelines for determining setup and hold times:
(a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL.
Publication Release Date: June 1999
Revision A4
- 13 -
WINBOND [ WINBOND ]
