W27C512
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27C512 has two control functions, both of which produce data
PP
CE
OE
/V controls the output buffer to gate data
at the outputs.
is for power control and chip select.
ACC
to the output pins. When addresses are stable, the address access time (T
) is equal to the delay
CE
OE
PP
/V ,
CE
OE
from
to output (T ), and data are available at the outputs T
after the falling edge of
ACC
CE
if T
and T timings are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27C512 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
PP
PE
CC
CE
PE
OE
Erase mode is entered when
/V is raised to V (14V), V
= V (5V), A9 = V (14V), A0
CE
low, and all other address pins low and data input pins high. Pulsing
operation.
low starts the erase
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
CC
successfully erased to "1" or not. The erase verify mode ensures a substantial erase margin if V
=
CE
V
PP
CE
OE
/V low.
(3.75V),
low, and
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only
PP
PP
OE
way to change cell data from "1" to "0." The program mode is entered when
/V is raised to V
= V (5V), the address pins equal the desired addresses, and the input pins equal the
CE
CC
(12V), V
CP
desired inputs. Pulsing
low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully
programmed with the desired data or not. Hence, after each byte is programmed, a program verify
operation should be performed. The program verify mode automatically ensures a substantial
PP
OE
CE
low.
program margin. This mode will be entered after the program operation if
/V low and
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
CE
data. When
CE OE
high, erasing or programming of non-target chips is inhibited, so that except for the
PP
and
/V pins, the W27C512 may have common inputs.
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