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W25Q128BV 参数 Datasheet PDF下载

W25Q128BV图片预览
型号: W25Q128BV
PDF下载: 下载PDF文件 查看货源
内容描述: 具有双路和四路SPI 3V 128M位串行闪存 [3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI]
分类和应用: 闪存
文件页数/大小: 74 页 / 756 K
品牌: WINBOND [ WINBOND ]
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W25Q128BV  
7.2.22 Quad Input Page Program (32h)  
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously  
erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can  
improve performance for PROM Programmer and applications that have slow clock speeds <5MHz.  
Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since  
the inherent page program time is much greater than the time it take to clock-in the data.  
To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write Enable  
instruction must be executed before the device will accept the Quad Page Program instruction (Status  
Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code  
“32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS pin must  
be held low for the entire length of the instruction while data is being sent to the device. All other functions  
of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction  
sequence is shown in Figure 20.  
/CS  
Mode 3  
Mode 0  
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31  
CLK  
IO0  
Instruction (32h)  
24-Bit Address  
23 22 21  
3
2
1
0
*
IO1  
IO2  
IO3  
= MSB  
*
/CS  
31 32 33 34 35 36 37  
Mode 3  
Mode 0  
CLK  
Byte  
253  
Byte  
254  
Byte  
255  
Byte  
256  
Byte 1  
Byte 2  
Byte 3  
0
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
0
1
2
3
4
5
6
0
1
2
3
4
0
1
2
3
4
0
1
2
3
IO0  
IO1  
IO2  
IO3  
5
6
5
6
5
6
7
7
7
7
7
7
7
*
*
*
*
*
*
*
Figure 20. Quad Input Page Program Instruction Sequence Diagram  
Publication Release Date: April 01, 2011  
Revision E  
- 41 -  
 
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