W25Q128BV
Table of Contents
1.
2.
3.
GENERAL DESCRIPTION ...............................................................................................................5
FEATURES.......................................................................................................................................5
PACKAGE TYPES AND PIN CONFIGURATIONS...........................................................................6
3.1
3.2
3.3
3.4
3.5
3.6
Pad Configuration WSON 8x6-mm ......................................................................................6
Pad Description WSON 8x6-mm..........................................................................................6
Pin Configuration SOIC 300-mil ...........................................................................................7
Pin Description SOIC 300-mil...............................................................................................7
Ball Configuration TFBGA 8x6-mm ......................................................................................8
Ball Description TFBGA 8x6-mm .........................................................................................8
4.
PIN DESCRIPTIONS........................................................................................................................9
4.1
4.2
4.3
4.4
4.5
Chip Select (/CS)..................................................................................................................9
Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3).....................................9
Write Protect (/WP) ..............................................................................................................9
HOLD (/HOLD) .....................................................................................................................9
Serial Clock (CLK)................................................................................................................9
5.
6.
BLOCK DIAGRAM..........................................................................................................................10
FUNCTIONAL DESCRIPTIONS.....................................................................................................11
6.1
SPI OPERATIONS .............................................................................................................11
6.1.1 Standard SPI Instructions.....................................................................................................11
6.1.2 Dual SPI Instructions............................................................................................................11
6.1.3 Quad SPI Instructions...........................................................................................................11
6.1.4 Hold Function .......................................................................................................................11
6.2
WRITE PROTECTION .......................................................................................................12
6.2.1 Write Protect Features .........................................................................................................12
7.
STATUS REGISTERS AND INSTRUCTIONS ...............................................................................13
7.1
STATUS REGISTERS........................................................................................................13
7.1.1 BUSY Status (BUSY)............................................................................................................13
7.1.2 Write Enable Latch Status (WEL) ........................................................................................13
7.1.3 Block Protect Bits (BP2, BP1, BP0)......................................................................................13
7.1.4 Top/Bottom Block Protect Bit (TB)........................................................................................13
7.1.5 Sector/Block Protect Bit (SEC).............................................................................................13
7.1.6 Complement Protect Bit (CMP) ............................................................................................14
7.1.7 Status Register Protect Bits (SRP1, SRP0)..........................................................................14
7.1.8 Erase/Program Suspend Status (SUS) ................................................................................14
7.1.9 Security Register Lock Bits (LB3, LB2, LB1)........................................................................14
7.1.10 Quad Enable Bit (QE).........................................................................................................15
7.1.11 Status Register Memory Protection (CMP = 0)...................................................................16
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