W25P022A
Timing Waveforms, continued
Write Cycle Timing
Single Write
Burst Write
Write
Unselected
TCYC
TKH
CLK
TKL
TADSS
TADSH
ADSP is blocked by CE1 inactive
ADSP
TADCH
TADVH
TADCS
ADSC initiated write
ADSC
TADVS
ADV
ADV must be inactive for ADSP write
WR2
TAS
TAH
A[15:0]
WR1
WR3
GWE allows processor address (and BE=BW)
to be pipelined during a writeback
TWS
TWS
TWS
TWH
GW
TWH
BWE
TWH
WR1
WR2
BW[4:1]
CE1
WR3
TCEH
TCES
CE1 masks ADSP
TCES
TCEH
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE2
CE2
TCES
TCEH
CE3
OE
Data-Out
High-Z
High-Z
TDS TDH
1a
BW[4:1] are applied only to first cycle of WR2
2a
2b
2c
2d
3a
Data-In
DON'T CARE
UNDEFINED
Publication Release Date: September 1996
Revision A1
- 11 -
WINBOND [ WINBOND ]
