ISD5100 – SERIES
3. BLOCK DIAGRAM
ISD5100-Series Block Diagram
FTHRU
6dB
INP
FILTO
SUM1
ANA OUT+
ANA OUT-
ANA
OUT
AMP
MICROPHONE
SUM1
Summing
AMP
INP
SUM2
Summing
AMP
MIC IN
AGC
MIC+
VOL
SUM2
FILTO
1
SUM1 MUX
Low Pass
Filter
Σ
SUM1
ARRAY
(AOPD)
MIC -
1
ANA IN
Σ
(AGPD)
S1M0
2
1
(FLPD)
1 (FLS0)
S2M0
S2M1
3
(
)
S1M1
AGCCAP
2
(
)
AOS0
AUX IN
FILTO
ANA IN
ARRAY
AOS1
( )
AOS2
1
(INS0)
Internal
Clock
AUX IN
Multilevel/Digital
Storage Array
AUX IN
AMP
1
(AXPD)
FLD0
FLD1
2
(
)
2
AUX
OUT
AMP
AXG0
S1S0
SUM2
Array I/OMux
FILTO
SUM2
2
(
)
(
)
(ANALOG)
AUX OUT
AXG1
S1S1
64-bit/samp.
64-bit/samp.
XCLK
CTRL
(DIGITAL)
SPEAKER
SP+
VOL
ARRAY OUTPUT MUX ARRAY OUT
ARRAY OUT
(ANALOG)
(DIGITAL)
Spkr.
AMP
ANA IN
ANA IN
AMP
ANA IN
SP-
1
2
SUM1
INP
ANA IN
(AIPD)
2
OPS0
Volume
(
)
OPA0
OPS1
VOL0
(
)
Control
OPA1
VOL1
AI2G0
AIG1
(V
LPD
)
VOL2
( )
1
3
(
)
SUM2
VLS0
VLS1
(
)
2
Power Conditioning
Device Control
VCCD
SDA
INT
RAC
A0
A1
VCCA VSSA VSSA VSSD
VCCD
SCL
VSSD
- 4 -
WINBOND [ WINBOND ]
