ISD5100 – SERIES
7.4.3. ISD5100 Series Aanalog Structure (right half) Description
FILTER
MUX
FILTO
FILTO
FILTER
SUM2 SUMMING
AMP
SUM1
LOW PASS
FILTER
SUM2
Σ
ARRAY
FLS0
0
1
SOURCE
SUM1
ARRAY
1
1
2 (S2M1,S2M0)
S2M1
S2M0
SOURCE
BOTH
ANA IN ONLY
FILTO ONLY
Power Down
(FLS0) (FLPD)
0
0
1
1
0
1
0
1
FLPD
0
1
CONDITION
Power Up
Power Down
ANA IN AMP
XCLK
MULTILEVEL
STORAGE
ARRAY
INTERNAL
CLOCK
FLD1
FLD0 SAMPLE FILTER
2
RATE
BANDWIDTH
3.6 KHz
(FLD1,FLD0)
0
0
1
1
0
1
0
1
8 KHz
6.4 KHz
5.3 KHz
4.0 KHz
2.9 KHz
2.4 KHz
1.8 KHz
ARRAY
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
VLS1
VLS0 VOL2 VOL1 VOL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD
CFG1
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