ISD5100 – SERIES
7.4.2. ISD5100 Series Analog Structure (left half) Description
INP
SUM1 SUMMING
AMP
INPUT
SO URCE
MUX
AGC AMP
SUM1
Σ
AUX IN AMP
2 (S1M1,S1M0)
(INS0) SUM1
MUX
FILTO
S1M1
S1M0
SOURCE
BOTH
SUM1 MUX ONLY
INP Only
Power Down
0
0
1
1
0
1
0
1
AN A IN AMP
ARRAY
INSO
0
1
Source
AGC AMP
AUX IN AMP
S1S1
S1S0
SOURCE
2 (S1S1,S1S0)
0
0
1
1
0
1
0
1
ANA IN
ARRAY
FILTO
N/C
1 5
14
13
12
1 1
10
9
8
7
6
5
4
3
2
1
0
AIG1
AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD CFG0
14 13 12 1 1 10
1 5
9
8
7
6
5
4
3
2
1
0
VLS1 VLS0 V OL2 VOL1 V OL0 S1S1 S1S0 S1M1 S1M0 S2M1 S2M0 FLS0 FLD1 FLD0 FLPD AGPD
CFG1
Publication Release Date: October, 2003
Revision 0.2
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