ISD5100 – SERIES
7.3.5. Configuration Resiter Bytes
The configuration register bytes are defined, in detail, in the drawings of section 7.4 on page 29. The
drawings display how each bit enables or disables a function of the audio paths in the ISD5100-
Series. The tables below give a general illustration of the bits. There are two configuration registers,
CFG0 and CFG1, so there are four 8-bit bytes to be loaded during the set-up of the device.
Configuration Register 0 (CFG0)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D 6 D5 D4 D3 D2 D1 D0
AIG1 AIG0 AIPD AXG1 AXG0 AXPD INS0 AOS2 AOS1 AOS0 AOPD OPS1 OPS0 OPA1 OPA0 VLPD
Volume Control Power Down
SPKR & AUX OUT Control (2 bits)
OUTPUT MUX Select (2 bits)
ANA OUT Power Down
AUXOUT MUX Select (3 bits)
INPUT SOURCE MUX Select (1 bit)
AUX IN Power Down
AUX IN AMP Gain SET (2 bits)
ANA IN Power Down
ANA IN AMP Gain SET (2 bits)
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WINBOND [ WINBOND ]
