ISD4004 SERIES
7.2.2. SPI Diagrams
LSB
A0
A15
C
0
C
4
X
X X
Input Shift Register
MOSI
(Loaded to Row Counter
only if IAB = 0)
A0-A15
Select Logic
Row Counter
P0-P15
LSB
OVF EOM P0 ...
MISO
Output Shift Register
P15
FIGURE 3: SPI INTERFACE SIMPLIFIED BLOCK DIAGRAM
The following diagram describes the SPI port and the control bits associated with it.
LSB
A0
MSB
C0 C1 C2 C3 C4
A1
A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
x
x
x
MOSI
Message Cueing (MC)
Ignore Address Bit (IAB)
Power Up (PU)
Play/Record (P/R)
RUN
LSB
OVF EOM P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
MSB
0
MISO
0
0
0
0
0
Notes: 1. For MOSI, LSB is the 1st bit shifted into the ISD4004.
2. For MISO, LSB is the 1st bit shifted out from the ISD4004.
FIGURE 4: SPI PORT
Publication Release Date: October 26, 2005
Revision 1.2
- 15 -
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