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25M02GVTCIG 参数 Datasheet PDF下载

25M02GVTCIG图片预览
型号: 25M02GVTCIG
PDF下载: 下载PDF文件 查看货源
内容描述: [3V 2G-BIT (2 x 1G-BIT) SERIAL SLC NAND FLASH MEMORY WITH DUAL/QUAD SPI BUFFER READ & CONTINUOUS READ CONCURRENT OPERATIONS]
分类和应用:
文件页数/大小: 68 页 / 820 K
品牌: WINBOND [ WINBOND ]
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W25M02GV  
8.2.21 Fast Read Quad Output (6Bh)  
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction  
except that data is output on four pins, IO0, IO1, IO2, and IO3. The Fast Read Quad Output Instruction  
allows data to be transferred at four times the rate of standard SPI devices.  
The Fast Read Quad Output instruction sequence is shown in Figure 24a & 24b. When BUF=1, the device  
is in the Buffer Read Mode. The data output sequence will start from the Data Buffer location specified by  
the 16-bit Column Address and continue to the end of the Data Buffer. Once the last byte of data is output,  
the output pin will become Hi-Z state. When BUF=0, the device is in the Continuous Read Mode, the data  
output sequence will start from the first byte of the Data Buffer and increment to the next higher address.  
When the end of the Data Buffer is reached, the data of the first byte of next memory page will be  
following and continues through the entire memory array. This allows using a single Read instruction to  
read out the entire memory array and is also compatible to Winbond’s SpiFlash NOR flash memory  
command sequence.  
When WP-E bit in the Status Register is set to a 1, this instruction is disabled.  
/CS  
Mode 3  
Mode 0  
0
7
8
9
21 22 23  
31 32 33 34 35 36 37 38 39 40  
CLK  
8 Dummy  
Clocks  
Instruction  
Column Address[15:0]  
15 14 13  
DI  
(IO0)  
2
1
0
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
6Bh  
High Impedance  
DO  
(IO1)  
High Impedance  
High Impedance  
IO2  
IO3  
7
7
7
7
7
*
*
*
*
*
Data  
Out 1  
Data  
Out 2  
Data  
Out 3  
Data  
Out 4  
Data  
Out 5  
= MSB  
*
Figure 24a. Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1)  
/CS  
Mode 3  
Mode 0  
0
7
8
9
21 22 23  
39 40 41 42 43 44 45 46 47 48  
CLK  
Instruction  
32 Dummy Clocks  
18 17 16  
DI  
(IO0)  
31 30 29  
0
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
6Bh  
High Impedance  
DO  
(IO1)  
High Impedance  
High Impedance  
IO2  
IO3  
7
7
7
7
7
*
*
*
*
*
Data  
Out 1  
Data  
Out 2  
Data  
Out 3  
Data  
Out 4  
Data  
Out 5  
= MSB  
*
Figure 24b. Fast Read Quad Output Instruction (Continuous Read Mode, BUF=0)  
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