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WCSS0418V1P-100BGC 参数 Datasheet PDF下载

WCSS0418V1P-100BGC图片预览
型号: WCSS0418V1P-100BGC
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×18的同步流水线高速缓存RAM [256K x 18 Synchronous-Pipelined Cache RAM]
分类和应用:
文件页数/大小: 17 页 / 662 K
品牌: WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
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WCSS0418V1P
Write Cycle Description
[4, 5, 6]
Function
Read
Read
Write Byte 0 - DQ
[7:0]
Write Byte 1 - DQ
[15:8]
Write Bytes 1, 0
Write Byte 2 - DQ
[23:16]
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 - DQ
[31:24]
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
Write All Bytes
GW
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
BWE
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
BW
3
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
BW
2
X
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
X
BW
1
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
BW
0
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied..................................................
−55°C
to +125°C
Supply Voltage on V
DD
Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[7]
....................................... −0.5V
to V
DD
+ 0.5V
DC Input Voltage
[7]
.................................... −0.5V
to V
DD
+ 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Com’l
Industrial
Ambient
Temperature
[8]
0°C to +70°C
–40°C to +85°C
V
DD
3.3V
−5%/+10%
V
DDQ
2.5V
−5%
3.3V +10%
Notes:
4. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW
[1:0]
. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ
[15:0]
;DP
[1:0]
= High-Z when OE is
inactive or when the device is deselected, and DQ
[15:0]
;DP
[1:0]
= data when OE is active.
7. Minimum voltage equals
−2.0V
for pulse durations of less than 20 ns.
8. T
A
is the case temperature.
Document #: 38-05247
Page 7 of 17