WCSS0418V1P
Switching Waveforms
Write Cycle Timing[14, 15]
Single Write
Burst Write
Pipelined Write
t
Unselected
CH
t
CYC
CLK
t
ADH
t
ADS
t
ADSP ignored with CE inactive
CL
1
ADSP
ADSC
ADV
t
ADH
t
ADSC initiated write
ADS
t
t
ADVH
ADVS
t
ADV Must Be Inactive for ADSP Write
WD2
AS
WD3
ADD
GW
WE
WD1
t
AH
t
WH
t
WH
t
WS
t
WS
t
t
CES
CEH
CE masks ADSP
1
CE
1
t
t
CEH
CES
Unselected with CE
2
CE
2
CE
3
t
CES
t
CEH
OE
t
DH
t
DS
High-Z
High-Z
Data
In
3a
2a
= UNDEFINED
1a
1a
2b
2c
2d
= DON’T CARE
Notes:
14. WE is the combination of BWE, BW[1:0], and GW to define a write cycle (see Write Cycle Description table).
15. WDx stands for Write Data to Address X.
Document #: 38-05247
Page 10 of 17
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
