WCSS0418V1P
Pin Definitions
(continued)
Name
ADSC
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A
[17:0]
is
captured in the address registers. A
[1:0]
are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. Leaving ZZ floating or NC will default the device into an active state.
ZZ pin has an internal pull-down.
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
A
[17:0]
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
[15:0]
and DP
[1:0]
are placed
in a three-state condition.
Power Supply Power Supply inputs to the core of the device. Should be connected to 3.3V power supply.
Ground
Ground for the core of the device. Should be connected to ground of the system.
I/O Power
Power Supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.
Supply
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
Input-
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
DDQ
or left
Static
floating selects interleaved burst sequence. This is a strap pin and should remain static during device
operation. When left floating or NC, defaults to interleaved burst order. Mode pin has an internal
pull-up.
No Connects.
is HIGH. The address presented to the address inputs (A
[17:0]
)
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The cor-
responding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE
1
, CE
2
, CE
3
are all asserted active. The address presented
to A
[17:0]
is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW
[1:0]
) and ADV inputs are ig-
nored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ
[15:0]
and DP
[1:0]
inputs is written into
the corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
BW
[1:0]
signals. The WCSS0418V1P provides byte write ca-
pability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BW
[1:0]
) input will selectively write to only the de-
sired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations.
Page 4 of 17
I/O
Input-
Synchronous
ZZ
DQ
[15:0]
DP
[1:0]
V
DD
V
SS
V
DDQ
V
SSQ
MODE
NC
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Max-
imum access delay from the clock rise (t
CO
) is 3.5 ns (166-MHz
device).
The WCSS0418V1P supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The in-
terleaved burst order supports Pentium and i486 processors.
The linear burst sequence is suited for processors that utilize
a linear burst sequence. The burst order is user selectable,
and is determined by sampling the MODE input. Accesses can
be initiated with either the Processor Address Strobe (ADSP)
or the Controller Address Strobe (ADSC). Address advance-
ment through the burst sequence is controlled by the ADV in-
put. A two-bit on-chip wraparound burst counter captures the
first address in a burst sequence and automatically increments
the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
[1:0]
) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchro-
nous self-timed write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. ADSP is ignored if CE
1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are sat-
isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE
1
, CE
2
, CE
3
are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE
1
Document #: 38-05247
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
