:
WCSS0232V1P
Linear Burst Sequence
First
Address
A
[1:0]
00
01
10
11
Second
Address
A
[1:0]
01
10
11
00
Third
Address
A
[1:0]
10
11
00
01
Fourth
Address
A
[1:0]
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ plac-
es the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE
1
, CE
2
, CE
3,
ADSP, and ADSC must remain inactive for the
duration of t
ZZREC
after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
Description
Snooze mode
standby current
Device operation to
ZZ
ZZ recovery time
Test Conditions
ZZ > V
DD
−
0.2V
ZZ > V
DD
−
0.2V
ZZ < 0.2V
2t
CYC
Min
Max
3
2t
CYC
Unit
mA
ns
ns
Cycle Descriptions
[1,2,3]
Next Cycle
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “sleep”
Add. Used
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
External
Next
Next
Current
Current
None
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
CE
3
X
1
X
1
X
0
0
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
CE
2
X
X
0
X
0
1
1
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
CE
1
1
0
0
0
0
0
0
X
X
1
1
X
X
1
1
X
1
0
X
1
X
1
X
ADSP
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
1
X
1
1
X
1
X
X
ADSC
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
X
ADV
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
1
1
X
0
0
1
1
X
OE
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Write
X
X
X
X
X
X
read
read
read
read
read
read
read
read
read
write
write
write
write
write
write
write
X
Notes:
1. X=”Don't Care”, 1=HIGH, 0=LOW.
2. Write is defined by BWE, BW
[3:0]
, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
