:
WCSS0232V1P
Pin Definitions
Pin Number
49–44, 81,82,
99, 100,
32–37
96–93
88
Name
A
[15:0]
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Description
Address Inputs used to select one of the 64K address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed the 2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
to the SRAM. Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BW
[3:0]
and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
signal must be asserted LOW to conduct a byte write.
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ignored if
CE
1
is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
2
to select/deselect the device.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first
clock of a read cycle when emerging from a deselected state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it auto-
matically increments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When assert-
ed LOW, A
[15:0]
is captured in the address registers. A
[1:0]
are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE
1
is deasserted HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When assert-
ed LOW, A
[15:0]
is captured in the address registers. A
[1:0]
are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical
“sleep” condition with data integrity preserved.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A
[15:0]
during the previous clock rise of the
read cycle. The direction of the pins is controlled by OE. When OE is asserted
LOW, the pins behave as outputs. When HIGH, DQ
[31:0]
are placed in a three-state
condition.
Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.
Ground for the I/O circuitry. Should be connected to ground of the system.
Selects burst order. When tied to GND selects linear burst sequence. When tied
to V
DDQ
or left floating selects interleaved burst sequence. This is a strap pin and
should remain static during device operation.
No Connects.
BW
[3:0]
GW
87
89
98
BWE
CLK
CE
1
97
92
86
CE
2
CE
3
OE
83
84
ADV
ADSP
Input-
Synchronous
Input-
Synchronous
85
ADSC
Input-
Synchronous
Input-
Asynchronous
I/O-
Synchronous
64
ZZ
29, 28,
DQ
[31:0]
25–22, 19,
18,13,12,
9–6, 3, 2, 79,
78, 75–72,
69, 68, 63, 62
59–56, 53, 52
15, 41, 65, 91 V
DD
17, 40, 67, 90
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 21, 26,
55, 60, 71, 76
31
V
SS
V
DDQ
V
SSQ
MODE
Power Supply
Ground
I/O Power
Supply
I/O Ground
Input-
Static
-
1, 14, 16, 30, NC
38, 39, 42, 43,
50, 51, 66, 80
3
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
