WCMA1008C1X
Switching Waveforms
Read Cycle No.1
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
t
RC
CE
1
CE
2
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
I
SB
I
CC
HIGH
IMPEDANCE
DATA OUT
Notes:
8. Full Device operatin requires linear V
CC
ramp from V
DR
to V
CC(min)
> 100
µ
s or stable at V
cc(min)
> 100
µ
s.
9. Device is continuously selected. OE, CE
1
= V
IL
, CE
2
= V
IH
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE
1
transition LOW and CE
2
transition HIGH.
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