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WCFS1008V1C-JC12 参数 Datasheet PDF下载

WCFS1008V1C-JC12图片预览
型号: WCFS1008V1C-JC12
PDF下载: 下载PDF文件 查看货源
内容描述: 128K ×8静态RAM [128K x 8 Static RAM]
分类和应用:
文件页数/大小: 8 页 / 175 K
品牌: WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
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WCFS1008V1C  
AC Test Loads and Waveforms  
R1 480 Ω  
ALL INPUT PULSES  
90%  
10%  
R1 480 Ω  
3.3V  
3.3V  
OUTPUT  
3.0V  
GND  
90%  
10%  
OUTPUT  
R2  
R2  
255 Ω  
30 pF  
5 pF  
255 Ω  
3 ns  
3 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(b)  
(a)  
THÉ  
Equivalent to:  
VENIN EQUIVALENT  
167 Ω  
1.73V  
OUTPUT  
Switching Characteristics[4] Over the Operating Range  
WCFS1008V1C 12ns  
Parameter  
Description  
Min.  
12  
3
Max.  
Unit  
READ CYCLE  
tRC  
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
12  
tOHA  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
OE HIGH to High Z[5, 6]  
CE LOW to Low Z[6]  
CE HIGH to High Z[5, 6]  
CE LOW to Power-Up  
CE HIGH to Power-Down  
tACE  
12  
6
tDOE  
tLZOE  
0
3
0
tHZOE  
6
6
tLZCE  
tHZCE  
tPU  
tPD  
12  
WRITE CYCLE[7, 8]  
tWC  
tSCE  
tAW  
tHA  
Write Cycle Time  
12  
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CE LOW to Write End  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
8
0
tSA  
0
tPWE  
tSD  
8
Data Set-Up to Write End  
Data Hold from Write End  
WE HIGH to Low Z[6]  
6
tHD  
0
tLZWE  
3
tHZWE  
WE LOW to High Z[5, 6]  
6
Notes:  
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
OL/IOH and 30-pF load capacitance.  
I
5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.  
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.  
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these  
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.  
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD  
.
3