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WED3EG6418S202D4 参数 Datasheet PDF下载

WED3EG6418S202D4图片预览
型号: WED3EG6418S202D4
PDF下载: 下载PDF文件 查看货源
内容描述: 128MB- 16Mx64 DDR SDRAM UNBUFFERED W / PLL [128MB- 16Mx64 DDR SDRAM UNBUFFERED W/PLL]
分类和应用: 存储内存集成电路动态存储器双倍数据速率
文件页数/大小: 7 页 / 81 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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WED3EG6418S-D4  
FINAL  
IDD SPECIFICATIONS AND TEST CONDITIONS  
(Recommended operating conditions, tA = 0 to 70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V)  
DDR333@CL=2.5 DDR266@CL=2, 2.5 DDR200@CL=2  
Parameter  
Symbol Conditions  
Units  
Max  
Max  
Max  
One device bank; Active = Precharge;  
tRC=tRC(MIN); tCK=tCK  
Operating Current  
IDD0  
(MIN); DQ, DM and DQS inputs changing  
once per clock cycle; Address and control  
inputs changing once every two cycles.  
840  
760  
680  
mA  
One device banks; Active-Read-Precharge;  
Burst = 2; tRC=tRC(MIN); tCK=tCK  
Operating Current  
IDD1  
IDD2P  
IDD2F  
IDD3P  
1040  
24  
960  
24  
880  
24  
mA  
mA  
mA  
mA  
(MIN); lOUT=0mA; Address and control inputs  
changing once per clock cycle.  
Precharge Power-  
Down Standby Current  
All device bank idle; Power-down mode;  
tCK=tCK(MIN); CKE=(low)  
CS# = High; All device banks idle;  
tCK=tCK(MIN); CKE = high; Address and other  
control inputs changing once per clock cycle.  
VIN = VREF for DQ, DQS and DM.  
Idle Standby Current  
200  
280  
180  
280  
160  
225  
Active Power-Down  
Standby Current  
One device bank active; Power-down mode;  
tCK(MIN); CKE=(low)  
CS# = High; CKE = High; One device  
bank; Active-Precharge; tRC=tRAS(MAX);  
tCK=tCK(MIN); DQ, DM and DQS inputs  
changing twice per clock cycle; Address and  
other control inputs changing once per clock  
cycle  
Active Standby Current  
IDD3N  
495  
440  
360  
mA  
Burst = 2; Reads; Continous burst; Once  
device bank active; Address and control  
inputs changing once per clock cycle;  
tCK=tCK(MIN); IOUT=0mA  
Burst=2; Writes; Continous burst; Once  
device bank active; Address and control  
inputs changing once per clock cycle;  
tCK=tCK(MIN); DQ,DM and DQS inputs  
changing twice per clock cycle.  
Operating Current  
Operating Current  
IDD4R  
1280  
1216  
1140  
1040  
960  
815  
mA  
mA  
IDD4W  
Auto Refresh Current  
Self Refresh Current  
IDD5  
IDD6  
1520  
16  
1440  
16  
1315  
16  
mA  
mA  
tRC=tRC(MIN)  
CKE £ 0.2V  
Four bank interleaving Reads (BL=4)  
with auto precharge with tRC=tRC(MIN);  
tCK=tCK(MIN); Address and control input  
change only during Active Read or Write  
commands.  
Operating Current  
IDD7A  
2640  
2400  
1920  
mA  
* Module IDD was calculated on the basis of component IDD and can be different measured according to DQ loading cap.  
White Electronic Designs Corp. reserves the right to change products or specifications without notice.  
Oct. 2002  
Rev. # 0  
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com