W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
READ COMMAND
ꢀhe READ command is used to initiate a burst read access
to an active row. ꢀhe value on the BA2–BA0 inputs selects
the bank, and the address provided on inputsA0–i (where
i = A9) selects the starting column location. ꢀhe value on
input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed
will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses.
FIGURE 11 – READ COMMAND
READ OPERATION
CK#
CK
READ bursts are initiated with a READ command. ꢀhe
starting column and bank addresses are provided with the
READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled,
the row being accessed is automatically precharged at the
completion of the burst. If auto precharge is disabled, the
row will be left open after the completion of the burst.
CKE
CS#
RAS#
CAS#
During READ bursts, the valid data-out element from the
starting column address will be available READ latency
(RT) clocks later. RT is defined as the sum of AT and CT;
RT = AT + CT. ꢀhe value for AT and CT are programmable
via the MR and EMR commands, respectively. Each
subsequent data-out element will be valid nominally at
the next positive or negative clock edge (i.e., at the next
crossing of CK and CK#).
WE#
ADDRESS
Col
ENABTE
A10
DQS/DQS# is driven by the DDR2 SDRAM along with
output data. ꢀhe initial TOW state on DQS and HIGH state
on DQS# is known as the read preamble (tRPRE). ꢀhe
TOW state on DQS and HIGH state on DQS# coincident
with the last data-out element is known as the read
postamble (tRPSꢀ).
AUꢀO PRECHARGE
BANK ADDRESS
DISABTE
Bank
DON’ꢀ CARE
Upon completion of a burst, assuming no other commands
have been initiated, the DQ will go High-Z.
Data from any READ burst may be concatenated with
data from a subsequent READ command to provide a
continuous flow of data. ꢀhe first data element from the
new burst follows the last element of a completed burst.
ꢀhe new READ command should be issued x cycles after
the first READ command, where x equals BT / 2 cycles.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
18
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
