W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes 1, 5, and 6 apply to all
CKE
BA2
BA1
BA0
A12
A11
Function
CS#
RAS#
CAS#
WE#
A10
A9-A0
Notes
Previous
Cycle
Current
Cycle
H
H
H
H
H
L
L
L
L
L
L
L
L
BA
X
OP Code
2
LOAD MODE
REFRESH
H
X
X
X
X
X
X
L
H
L
L
X
H
L
L
X
H
H
H
X
H
L
X
SELF-REFRESH Entry
L
H
X
X
X
X
7
2
SELF-REFRESH Exit
H
H
H
H
H
H
L
X
X
X
X
L
H
X
X
Single bank precharge
All banks PRECHARGE
Bank activate
L
L
L
L
H
H
L
L
BA
Row Address
Column
Address
Column
Address
Column
Address
Column
Address
Column
Address
Column
Address
Column
Address
Column
Address
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
L
L
L
L
BA
BA
BA
BA
L
H
L
2, 3
2, 3
2, 3
2, 3
WRITE
WRITE with auto precharge
READ
H
L
L
H
H
L
H
H
H
READ with auto precharge
H
H
X
X
H
X
X
X
X
X
X
X
X
NO OPERATION
H
H
L
H
L
X
X
H
X
H
X
X
H
X
H
X
X
H
X
H
Device DESELECT
H
L
X
X
X
X
X
X
X
4
4
POWER-DOWN entry
L
H
X
POWER-DOWN exit
Note: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.
3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC
parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.
6. “X” means “H or L” (but a defined logic level).
7. Self refresh exit is asynchronous.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
16
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
