EDI2CG472128V
White Electronic Designs
ADVANCED
SYNC-BURST READ CYCLE
tKHKH
t
KHKL KLKH
t
CK
t
SPVKH
tKHSPX
ADSP#
t
SCVKH
tKHSCX
ADSC#
ADDR
t
AVKtHKHAX
BWx,
GW#
tEVKH
tKHEX
Ex#
tAVVKH
tKHAVX
ADV#
G#
tGHQX
tKHQV
t
GLQV
tGHQZ
t
GLQX
DQ
tKHQX
tKHQX
Burst Read Cycle
Read Cycle
WRITE CYCLE TIMING PARAMETERS
8.5ns
10ns
12ns
Max
15ns
Min Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
Description
Sym
tKHKH
Min
Max
Min
Max
Min
Clock Cycle Time
Clock High Time
Clock Low Time
Address Setup
*
*
*
*
*
*
*
*
*
*
*
*
15
15
20
6
6
tKHKL
tKLKH
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tDVKH
tKHDX
*
*
*
*
*
*
*
*
*
*
5
5
5
5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
Address Hold
Bank Enable Setup
Bank Enable Hold
Global Write Enable Setup
Global Write Enable Hold
Data Setup
ns
ns
ns
Data Hold
*TBD
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 1999
Rev 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
